In semiconductor processing, SOI (semiconductor-on-insulator) technology is becoming increasingly important since it permits the formation of high-speed integrated circuits. In SOI technology, a relatively thin layer of semiconducting material, e.g., Si, overlays a layer of insulating material (e.g., a buried oxide region). This relatively thin layer of semiconducting material is generally the area wherein active devices are formed in SOI devices. Devices formed on SOI offer many advantages over their bulk Si counterparts; including higher performance, absence of latch-up, higher packing density and low voltage applications.
Despite the advantages obtained using SOI technology, SOI circuits, like other electronic devices, are susceptible to damage from electrostatic discharge (ESD). ESD is a transient surge in voltage (negative or positive) that may induce a large current in the circuit. To protect circuits against damage from ESD, protection schemes attempt to provide a discharge path with a low voltage turn-on and a high current capacity (the ability to generate or sink a large amount of current before a large amount of negative or positive voltage is developed). Discharge paths using traditional bulk devices (such as diodes) do not work well on SOI devices because of the presence of a relatively thin SOI buried oxide layer. That is, conventional diodes on SOI devices have small current capacity because the current is carried laterally through an active device region of limited thickness.
One approach for protecting SOI circuitry from ESD is found in U.S. Pat. No. 4,989,057 to Lu. Lu discloses a SOI diode, which could be used for ESD design. The SOI diode disclosed in Lu consists of a floating-body SOI transistor, with the gate connected to a signal pad. However, the Lu diode itself may have a thin insulating layer that is susceptible to damage from relatively moderate voltage differences. To provide diode operation, Lu shorts the gate to the cathode. Nevertheless, the Lu diode may not be suitable for usage in a mixed-voltage environment because the voltage difference between the gate and the anode may be sufficient to damage the insulating layer. This damage may lead to early ESD failures. This problem is not limited to SOI devices. Rather, it exists in bulk Si devices as well.